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MOSEL VITELIC
V53C816H 512K X 16 FAST PAGE MODE CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
40
40 ns 20 ns 23 ns 75 ns
45
45 ns 22 ns 25 ns 80 ns
50
50 ns 24 ns 28 ns 90 ns
60
60 ns 30 ns 35 ns 110 ns
Features
s 512K x 16-bit organization s RAS access time: 40, 45, 50, 60 ns s Fast Page Mode for a sustained data rate of 43 MHz s Dual CAS Inputs s Pin-to-Pin compatible with 256Kx16 s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh s Refresh Interval: 512 cycles/8 ms s Available in 40-pin 400 mil SOJ s Single +5V Power Supply s TTL Interface
Description
The V53C816H is a 524,288 x 16 bit high-performance CMOS dynamic random access memory. The V53C816H offers Fast Page mode with dual CAS inputs. An address, CAS and RAS input capacitances are reduced to one half when the 256Kx16 DRAM is used to construct the same memory density. The V53C816H has asymmetric address, 10-bit row and 9-bit column. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 512K x 16 bits, within a page, with cycle times as short as 23ns. The V53C816H is best suited for graphics, and buffer memory applications.
Device Usage Chart
Operating Temperature Range 0C to 70 C Package Outline K * 40 * Access Time (ns) 45 * 50 * 60 * Power Std. * Temperature Mark Blank
V53C816H Rev. 1.3 February 1999
1
MOSEL VITELIC
V 53
MOSEL-VITELIC MANUFACTURED 53 = DRAM C = CMOS PROCESS 8 = 8M-BIT
V53C816H
C 8 16 H K
HIGH PERFORMANCE BLANK = 5V DATA WIDTH: 16 = 16-BIT FP
SPEED 40 ns 45 ns 50 ns 60 ns
Description SOJ
Pkg. K
Pin Count 40
PACKAGE TYPE K = SOJ
816H-01
40-Pin SOJ PIN CONFIGURATION Top View
Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 NC NC WE RAS A9 A0 A1 A2 A3 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
816H-02
Pin Names
A0-A9 RAS Address Inputs, A9 is effective with RAS Row Address Strobe Column Address Strobe Upper Byte Control Column Address Strobe Lower Byte Control Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect
Vss I/O15 I/O14 I/O13 I/O12 Vss I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss
UCAS LCAS WE OE I/O0-I/O15 VCC VSS NC
V53C816H Rev. 1.3 February 1999
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MOSEL VITELIC
Absolute Maximum Ratings*
Ambient Temperature Under Bias .............................. -10C to +80C Storage Temperature (plastic) ..... -55C to +125C Voltage Relative to VSS .................-1.0 V to +7.0 V Data Output Current ..................................... 50 mA Power Dissipation .......................................... 1.4 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
V53C816H
Capacitance*
TA = 25C, VCC = 5 V 10%, f = 1 MHz
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. 3 4 5 Max. 4 5 7 Unit pF pF pF
* Note: Capacitance is sampled and not 100% tested
Block Diagram
512K x16
OE WE UCAS LCAS RAS
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VCC
DATA I/O BUS COLUMN DECODERS
Y0 -Y 8
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5
SENSE AMPLIFIERS REFRESH COUNTER
512 x 16 10 A0 A1
* * *
I/O BUFFER
I/O 6 I/O 7 I/O 8 I/O 9 I/O 10
ADDRESS BUFFERS AND PREDECODERS
X 0 -X 9
ROW DECODERS
1024
MEMORY ARRAY 512K x 16
I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
816H-03
A7 A8 A9
V53C816H Rev. 1.3 February 1999
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MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0C to 70C, VCC = 5 V 5%, VSS = 0 V, unless otherwise specified. Access Time V53C816H Min.
-10
V53C816H
Symbol
ILI ILO ICC1
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating
Typ.
Max.
10
Unit
A A mA
Test Conditions
VSS VIN VCC VSS VOUT VCC RAS, CAS at VIH tRC = tRC (min.)
Notes
-10
10
40 45 50 60
220 210 200 190 4
1, 2
ICC2 ICC3
VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 40 45 50 60
mA
RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2
220 210 200 190 210 200 190 180 2.0
mA
ICC4
VCC Supply Current, Fast Page Mode Operation
40 45 50 60
mA
Minimum Cycle
1, 2
ICC5
VCC Supply Current, Standby, Output Enabled other inputs VSS VCC Supply Current, CMOS Standby
mA
RAS=VIH, CAS=VIL
1
ICC6
2.0
mA
RAS VCC - 0.2 V, CAS VCC- 0.2 V, All other inputs VSS
VCC VIL VIH VOL VOH
Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
4.5 -1 2.4
5.0
5.5 0.8 VCC+1 0.4
V V V V V IOL = 2.0 mA IOH = -2.0 mA 3 3
2.4
V53C816H Rev. 1.3 February 1999
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MOSEL VITELIC
AC Characteristics
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V 40 #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
V53C816H
45
50
60
Symbol
tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH (R) tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD tRSH (W) tCWL tWCS tWCH tWP tWCR tRWL
Parameter
RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address OE or CAS to Low-Z Output OE or CAS to High-Z Output Column Address Hold Time from RAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time Write Pulse Width Write Command Hold Time from RAS Write Command to RAS Lead Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
40 75 25 40 12 17 0 0 7 0 5 12 5 0 28 75 45 80 25 45 13 18 0 0 8 0 6 13 5 0 32 75K 50 90 30 50 14 19 0 0 9 0 7 14 5 0 36 75K 60 110 40 60 15 20 0 0 10 0 10 15 5 0 45 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 4
15
0
0
0
0
ns
5
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
8 12 12 40 20 0 0 30 12 12 12 0 5 5 30 12 20 6
9 13 13 45 22 0 0 35 13 13 13 0 6 6 35 13 23 7
10 14 14 50 24 0 0 40 14 14 14 0 7 7 40 14 26 8
10 15 15 60 30 0 0 50 15 15 15 0 10 10 50 15 30 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12, 13 11 6, 7 6, 8, 9 6, 7, 10 16 16
V53C816H Rev. 1.3 February 1999
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MOSEL VITELIC
AC Characteristics (Cont'd)
40 #
32 33 34 35 36 37 38 39
V53C816H
45
50
60
Symbol
tDS tDH tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tT tREF
Parameter
Data in Setup Time Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in Read-Modify-Write Cycle CAS Pulse Width (RMW) Col. Address to WE Delay Fast Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS-before-RAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-before-RAS Refresh Fast Page Mode Read-Modify-Write Cycle Time Transition Time (Rise and Fall) Refresh Interval (512 Cycles)
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
0 5 6 6 110 75 30 58 0 6 7 7 115 80 32 62 0 7 8 8 130 87 34 68 0 10 10 10 155 105 40 85 ns ns ns ns ns ns ns ns 12 12 14 14 14 14
40 41 42 43 44 45
48 38 23 5 20 22
50 41 25 6 22 24
52 42 28 7 24 27
65 58 35 10 30 34
ns ns ns ns ns ns 7 12
46 47
30 10
35 10
40 10
50 10
ns ns
48 49
0 8
0 10
0 12
0 15
ns ns
50
60
65
70
85
ns
51 52
3 8
50
3 8
50
3 8
50
3 16
50
ns 8
15 17
V53C816H Rev. 1.3 February 1999
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MOSEL VITELIC
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in Fast Page Mode.
V53C816H
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to one TTL input and 50 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C816H Rev. 1.3 February 1999
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MOSEL VITELIC
Truth Table
Function
Standby Read: Word Read: Lower Byte
V53C816H
RAS
H L L
LCAS
H L L
UCAS
H L H
WE
X H H
OE
X L L
ADDRESS I/O
High-Z ROW/COL ROW/COL Data Out Lower Byte, Data-Out Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-Out Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-In Data-Out, Data-In Data-Out High-Z High-Z
Notes
Read: Upper Byte
L
H
L
H
L
ROW/COL
Write: Word (Early-Write) Write: Lower Byte (Early)
L L
L L
L H
L L
X X
ROW/COL ROW/COL
Read: Upper Byte (Early)
L
H
L
L
X
ROW/COL
Read-Write Fast Page-Mode Read Fast Page-Mode Write Fast Page-Mode Read-Write Hidden Refresh Read RAS-Only Refresh CBR Refresh
L L L L LHL L HL
L HL HL HL L H L
L HL HL HL L H L
HL H L HL H X X
LH L X LH L X X
ROW/COL COL COL COL ROW/COL ROW
1, 2 2 2 1, 2 2
3
Notes:
1. Byte write cycles LCAS or UCAS active. 2. Byte Read cycles LCAS or UCAS active. 3. Only one of the two CAS must be active (LCAS or UCAS).
V53C816H Rev. 1.3 February 1999
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MOSEL VITELIC
Waveforms of Read Cycle
t RC (2) VIH V IL t CSH (4) t CRP (13) CAS V IH V IL t ASR (8) ADDRESS V IH V IL ROW ADDRESS t RAD (24) t RAH (9) t ASC (10) COLUMN ADDRESS t CAR (44) t RCS (7) WE V IH V IL t CAA (20) OE V IH V IL t CAC (18) tRAC (19) I/O VOH VOL t LZ (21) t HZ (22) VALID DATA-OUT t OAC (17) t ROH (16) t RRH (15) t CAH (11) tRCD (6) t RSH (R)(12) t CAS (5) tAR (23) t RAS (1) t RP (3)
V53C816H
RAS
t CRP (13)
t RCH (14)
tHZ (22)
816H-04
Waveforms of Early Write Cycle
t RC (2) t RAS (1) RAS VIH V IL t CSH (4) t CRP (13) CAS VIH V IL t RAH (9) t ASR (8) ADDRESS VIH V IL ROW ADDRESS t RAD (24) tASC (10) COLUMN ADDRESS t WCH (28) t CAR (44) t CAH (11) tRCD (6) tRSH (W)(25) t CAS (5) t CRP (13) tAR (23) t RP (3)
t CWL (26) t WP(29) t WCS (27)
WE
VIH V IL
t WCR (30) t RWL (31) OE VIH V IL t DHR (46) t DS (32) I/O VIH V IL t DH (33) VALID DATA-IN HIGH-Z
816H-05
Don't Care
V53C816H Rev. 1.3 February 1999
Undefined
9
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
t RC (2) t RAS (1) RAS VIH V IL t CRP (13) CAS V IH V IL t RAD (24) t RAH (9) t ASR (8) ADDRESS V IH V IL ROW ADDRESS t CAR (44) t CAH (11) t ASC (10) COLUMN ADDRESS t CWL (26) t RWL (31) t WP (29) WE V IH V IL t WOH (34) OE V IH V IL t OED (35) V IH V IL t DH (33) t DS (32) VALID DATA-IN t CSH (4) t RCD (6) t RSH (W)(12) t CAS (5) t AR (23) t RP (3)
V53C816H
t CRP (13)
I/O
816H-06
Waveforms of Read-Modify-Write Cycle
t RWC (36) tRRW (37) RAS VIH VIL t CSH (4) t CRP (13) CAS VIH VIL t RAH (9) t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t RWD (39) WE VIH VIL VIH VIL t OED (35) t CAC (18) t RAC (19) I/O VIH VOH VIL VOL t LZ (21) VALID DATA-OUT t HZ (22) t DS (32) VALID DATA-IN
816H-07
t RP (3)
t AR (23)
t RCD (6)
t RSH (W)(25) t CRW (40) t t ASC (10) COLUMN ADDRESS t AWD (41) t CWD (38) t RWL (31) t CWL (26)
t CRP (13)
CAH (11)
t WP (29)
t CAA (20) t OAC (17)
OE
t DH (33)
Don't Care
V53C816H Rev. 1.3 February 1999
Undefined
10
MOSEL VITELIC
Waveforms of Fast Page Mode Read Cycle
RAS V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t RAH (9) t CSH (4) t ASC (10) t CAH (11) COLUMN ADDRESS t RCH (14) t CAH (11) t CAA (20) t OAC (17) OE V IH V IL t RAC (19) t CAC (18) t LZ (21) t HZ (22) t CAC (18) t HZ (22) t LZ (21) I/O V OH V OL VALID DATA OUT VALID DATA OUT t LZ (21) t CAC (18) t HZ (22) t HZ (22) t RCS (7) t CAR (44) t CAH (11) COLUMN ADDRESS t RCS (7) t PC (42) t CP (43) t RSH (R)(12) t CAS (5) t CRP (13) t CAS (5) t AR (23) t RAS (1) t
V53C816H
RP (3)
t CAS (5)
t ASR (8) ADDRESS V IH V IL
t ASC (10) ROW ADDRESS t RCS (7)
COLUMN ADDRESS
t RCH (14)
WE
V IH V IL t CAP (45) t OAC (17) t CAA (20) t OAC (17) t RRH (15)
t HZ (22) t HZ (22)
VALID DATA OUT
816H-08
Waveforms of Fast Page Mode Write Cycle
t AR (23) RAS V IH V IL t CRP (13) t RCD (6) CAS V IH V IL t RAH (9) t ASR (8) ADDRESS V IH V IL t RAD (24) t WCS (27) t WP (29) WE V IH V IL VIH V IL t DS (32) I/O V IH V IL
VALID DATA IN ROW ADD COLUMN ADDRESS
t RP (3) t RAS (1)
t PC (42) t CP (43) t CAS (5)
t RSH (W)(25) t CAS (5) t CAS (5)
t CRP (13)
t CSH (4) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
t CWL (26)
t WCH (28)
t WCS (27)
t CWL (26)
t WCH (28) t WP (29)
t WCS (27)
t CWL (26) t RWL (31) t WCH (28) t WP (29)
OE
t DS (32) t DH (33)
OPEN VALID DATA IN
t DS (32) t DH (33)
VALID DATA IN
t DH (33)
OPEN
816H-09
Don't Care
V53C816H Rev. 1.3 February 1999
Undefined
11
MOSEL VITELIC
Waveforms of Fast Page Mode Read-Write Cycle
RAS VIH V
IL
V53C816H
t RAS (1)
t RCD (6)
t CSH (4) t PCM (50) t CAS (5)
t RP (3) t RSH (W)(25) t CRP (13) t CAS (5)
t CP (43) t CAS (5)
V CAS V
IH IL
t RAD (24) t RAH (9) t ASR (8) t ASC (10) t ASC (10)
COLUMN ADDRESS
t CAH (11)
COLUMN ADDRESS
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
V ADDRESS V
IH IL
ROW ADD
t RCS (7) V WE V
IH IL
t RWD (39) t CWD (38)
t CWL (26)
t CWD (38) t CWL (26)
t CWD (38) t RWL (31) t CWL (26)
t CAA (20) t OAC (17) V OE V
IH IL
t AWD (41)
t AWD (41) t WP (29) t OAC (17)
t AWD (41) t OAC (17) t WP (29) t WP (29)
t OED (35) t CAC (18) t RAC (19)
t CAA (20)
t CAP (45)
t OED (35) t CAC (18) t DH (33)
t CAP (45) t CAA (20)
t HZ (22)
t HZ (22)
t DS (32) I/O V I/OH V I/OL t LZ (21)
OUT IN OUT
t DH (33) t DS (32)
t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32)
OUT IN
IN
t LZ (21)
t LZ (21)
816H-10
Waveforms of RAS-Only Refresh Cycle
tRC (2) VIH V IL t CRP (13) CAS VIH V IL tASR (8) ADDRESS VIH V IL NOTE: WE, OE = Don't care ROW ADDR
816H-11
t RAS (1)
tRP (3)
RAS
tRAH (9)
Don't Care
V53C816H Rev. 1.3 February 1999
Undefined
12
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1) RAS VIH V IL t CSR (47) CAS VIH V IL VIH V IL READ CYCLE WE VIH V IL t ROH (16) t OAC (17) OE VIH V IL t LZ (21) I/O VIH V IL WRITE CYCLE WE VIH V IL VIH V IL tDS (32) I/O VIH V IL t DH (33) D IN t RWL (31) t CWL (26) t WCS (27) t WCH (28) DOUT t CHR (49) t CP(43) t RSH (W)(25) tCAS (5)
V53C816H
t RP (3)
ADDRESS
t RCS (7)
t RRH (15) t RCH (14)
t HZ (22) t HZ (22)
OE
816H-12
Waveforms of CAS-before-RAS Refresh Cycle
t RP (3) RAS V IH V IL t CP (43) V IH V IL t HZ (22) I/O V OH V OL NOTE: WE, OE, A0-A8 = Don't care
816H-13
t RC (2) t RAS (1) t RP (3)
t RPC (48) t CSR (47)
t CHR (49)
CAS
Don't Care
V53C816H Rev. 1.3 February 1999
Undefined
13
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2) V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL t CAA (20) t OAC (17) OE V IH V IL t CAC (18) t LZ (21) t RAC (19) V OH I/O V OL VALID DATA t HZ (22) t HZ (22)
ROW ADD
V53C816H
t RC (2) tRP (3) t RAS (1) t RP (3)
t RAS (1) t AR (23)
RAS
t RSH (R)(12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10) t CAH (11)
COLUMN ADDRESS
t RCS (7) WE
t RRH (15)
816H-14
Waveforms of Hidden Refresh Cycle (Write)
t RC (2) V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL V IH V IL t DS (32) V IH I/O V IL t DH (33)
VALID DATA-IN ROW ADD
t RC (2) t RP (3) t RAS (1) t RP (3)
t RAS (1) t AR (23)
RAS
t RSH (12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10) t CAH (11)
COLUMN ADDRESS
t WCS (27) WE
t WCH (28)
OE
t DHR (46)
816H-15
Don't Care
V53C816H Rev. 1.3 February 1999
Undefined
14
MOSEL VITELIC
Functional Description
The V53C816H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C816H reads and writes data by multiplexing an 19-bit address into a 10-bit row and a 9-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address "flows through" an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time.
V53C816H
Fast Page Mode Operation
Fast Page Mode operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer and acts as an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or ReadWrite-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Fast Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. Fast Page Mode provides a sustained data rate of 43 MHz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 512 Data Rate = ---------------------------------------t RC + 511 x t PC
Memory Cycle
A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied.
Data Output Operation
The V53C816H Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal has no effect on
V53C816H Rev. 1.3 February 1999
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MOSEL VITELIC
any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied.
V53C816H
Table 1. V53C816H Data Output
Operation for Various Cycle Types
Cycle Type Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles Fast Page Mode Read Fast Page Mode Write Cycle (Early Write) Fast Page Mode ReadModify-Write Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles I/O State Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z
Power-On
After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C816H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
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MOSEL VITELIC
Package Diagram
40-Pin Plastic SOJ
1.025 TYP. (1.035 MAX.) [26.04 TYP. (26.29 MAX.)] 40 21 Unit in inches [mm]
V53C816H
0.400 0.005 [10.16 0.127]
0.440 0.005 [11.18 0.127]
1
20 0.026 MIN [0.660 MIN] 0.144 MAX [3.66 MAX]
0.010
+ 0.004 - 0.002
+0.004 0.025 -0.002
+0.102 0.635 -0.051
+0.102 0.254 -0.051
0.050 0.006 [1.27 0.152]
0.04 [0.1]
0.018
+0.004 -0.002
+0.102 0.457 -0.051
V53C816H Rev. 1.3 February 1999
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0.368 0.010 [9.35 0.254]
MOSEL VITELIC
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V53C816H
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(c) Copyright 1999, MOSEL VITELIC Inc.
2/99 Printed in U.S.A.
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